1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to integrated circuit fabrication processes and structures.
2. Description of the Background Art
Typical integrated circuit devices have a seal ring that encompasses an active area of a die. The seal ring, also referred to as a “guard ring,” protects circuitry in the active area from ionic contamination and moisture penetration. The seal ring also helps prevent cracks from propagating to the active area during the dicing process.
FIG. 1 schematically shows an example conventional seal ring 100. Seal ring 100 includes several seal ring metal layers 102 (i.e. 102-1, 102-2, . . . ) that are electrically coupled together by vias 103. One or more dielectric layers 106, which are not individually delineated in FIG. 1 for clarity of illustration, are formed between metal layers 102. As shown in FIG. 1, the metal layers 102 are formed such that an overlying metal layer 102 is wider than a metal layer 102 below it. The last metal layer 102, which is metal layer 102-1 in FIG. 1, is electrically connected to a semiconductor substrate 101.
The seal ring 100 also includes a shallow moat 104. Generally speaking, a moat is a trench formed in the seal ring to prevent cracks from propagating into the active area of the die (not shown). FIG. 2 shows an electron microscope image of an example conventional shallow moat 201. As noted in FIG. 2, the shallow moat 201 is 1.35 microns deep, 2.22 microns wide at the opening, and 1.86 microns wide at the bottom.
One problem with the seal ring 100 is that it is ineffective in capturing most cracks originating from the edge of the die. Another problem with the seal ring 100 is that as device size is reduced, the size of the vias 103 is also reduced. Yet another problem with the seal ring 100 is that the width of the seal ring 100 increases with the number of metal layers 102. This makes the seal ring 100 less desirable for multi-level metal technologies.